Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer
نویسندگان
چکیده
منابع مشابه
High-SFDR and Multiplierless Direct Digital Frequency Synthesizer
This paper presents a hybrid COordinate Rotation DIgital Computer (CORDIC) algorithm for designs and implementations of the direct digital frequency synthesizer (DDFS). The proposed multiplier-less architecture with small ROM ( 4 16× -bit) and pipelined data path provides a spurious free dynamic range (SFDR) of more than 84.4 dBc. A SoC (System on Chip) has been designed by m . μ 18 0 1P6M CMOS...
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ژورنال
عنوان ژورنال: IEEE Access
سال: 2020
ISSN: 2169-3536
DOI: 10.1109/access.2020.2986016